Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions are shrinking while wafer size is increasing. Economics is driving the industry to decrease the time for achieving high-yield, high-value production. Thus, minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for the semiconductor manufacturer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Finding a defect of interest (DOI) can be challenging. High nuisance rates are a common problem. Nuisance events can be misidentified as DOI or can cause a DOI to be incorrectly identified as a nuisance. Thus, nuisance events can make it difficult or even impossible to track DOI or monitor excursions. Consequently, killer defects that may jeopardize yield may be missed.
Nuisance events are common with wafers that include metal lines or lines of other materials. Due to the resolution limits of optical tools, the lines can appear blurry. This blurriness makes it difficult to determine if the defect falls on the line or not.
Previous techniques to find DOI on a wafer with metal lines were based on pattern (context) based attributes, such as by using the grey level. Pattern based attributes compare the optical image of a pattern to a nuisance pattern. The nuisance pattern is known to cause multiple nuisance events. These patterned based attribute techniques tend to be too inaccurate to sort patterns with high versus low numbers of nuisance events because these techniques require larger field of views and are limited to how well the patterns are optically resolved. The resolution using these techniques typically was an order of magnitude short. For example, defects were identified ±4 pixels. Thus, if each pixel was 50 nm, then defects were identified ±200 nm.
Another previous technique was based on defining very small care areas (CAs) around nuisance structures to filter out the nuisance structures. However, creating such CAs is time-consuming. The time required to perform this technique can be extremely large when rules need to be created to search for such CAs.
Therefore, an improved technique and system for nuisance reduction is needed.